Receptacle for a programmable, electronic processing device

ABSTRACT

A processing device embodied in an integrated circuit may be divided into first and second functional units. A mount for the integrated circuit may be assigned to the first functional unit, which may define the external electrical connections of the processing device. Processing may take place in a second functional unit of the processing device, whose essential connections may normally be accessible from outside via the external connections of the first functional unit. The processor device having first and second functional units in a mount may be similar to a hybrid circuit but may serve a different purpose. The first functional unit, which may also comprise more than one monolithic integrated circuit, may define the external connections and may make available suitable matching circuits for the second functional unit. In this manner, the processing device, which may be contained in the second functional unit and may also comprise more than one monolithic integrated circuit, may be considered to be “masked” as viewed from outside. In addition to the matching circuits, the first functional unit may contain subcircuits performing more general functions, such as oscillators, supply voltage regulator circuits, buffer circuits, protective circuits, etc.

BACKGROUND OF THE INVENTION

This invention relates in general to integrated circuits, and inparticular to a mount for a programmable electronic processing device.

Processing devices may constitute a processor which comprises at leastone structure in the form of a monolithic integrated circuit. Bothanalog and digital signals or data may be processed, depending on theapplication. The relatively small electronic processor modules allow theprocessors to be housed along with additional circuits, such asmemories, in a relatively small package. The relatively small packagedimensions are a characteristic of microprocessors. If at least twoindividual structures are contained in a mount, this may be referred toas a hybrid circuit, as distinguished from those cases where only asingle monolithic integrated circuit may be present.

The use of microprocessors is increasing in all areas of technology,since they readily lend themselves to embodiments of various controlprocesses. The cost and complexity of microprocessors is relatively low,and they allow for decentralized solutions. A wide range ofmicroprocessor applications is in mechanical engineering, particularlyin the automotive field, which is increasingly resorting tomicroprocessors to improve the behavior of various vehicle systems,subsystems and components.

In many cases where such processors can be used, however, a basicproblem arises from the fact that the technology life cycle times maydiffer widely for the manufacturer and user of the processors. When suchprocessors are adopted for use in a technical system, as uniform aproduct as possible should be available not only for the manufacture butalso for replacement throughout the development, planning, fabrication,and operating lifetimes of the associated system.

In the event of a technology change, aside from the changes inelectrical connection parameters, the potentially changed sensitivitiesto overvoltages, polarity reversals, and electromagnetic interferencehave to be taken into account. There are also changes in the interferingeffect on other circuits, for example by steeper clock-pulse and dataedges which travel as electromagnetic interference signals overrelatively long lines.

The pace of development in semiconductor technology is generally aheadof the time frame specified by the user, primarily because thedevelopment must follow then-current technology changes to be able toimplement increasingly complex circuits. The continued use of obsoletetechnologies involves the use of parallel production lines, which areusually uneconomical because full capacity utilization is not ensured.

What is needed is a mount for a processing device which enables thesemiconductor manufacturer, on the one hand, to use state-of-the-artsemiconductor processes and, on the other hand, to allow the product tobe used for a relatively long time.

SUMMARY OF THE INVENTION

A mount and a processing device may be somewhat dependent, since themount may be assigned a first functional unit of the processing device.As such, the first functional unit may define the external electricalconnections of the processing device. Processing may take place in asecond functional unit of the processing device, whose essentialconnections may normally be accessible from outside via the externalconnections of the first functional unit. The term “essentialconnections” as used herein may be understood to include thoseconnections which, as seen from outside, may be relatively critical interms of their electrical parameters because their tolerances are tightor because their active or passive disturbance behavior has to be takeninto account. Relatively uncritical connections, such as set or resetinputs, may be included but need not necessarily be routed via the firstfunctional unit, even though doing so may be safer in the long run inview of the foreseeable development of the technology used.

The processor device arrangement comprising first and second functionalunits in a mount may be similar to a hybrid circuit but may serve adifferent purpose. The first functional unit, which may also comprisemore than one monolithic integrated circuit, may define the externalconnections and may make available suitable matching circuits for thesecond functional unit. In this manner, the processing device, which maybe contained in the second functional unit and may also comprise morethan one monolithic integrated circuit, may be considered to be “masked”as viewed from outside. In addition to the matching circuits, the firstfunctional unit may contain subcircuits performing more generalfunctions, such as oscillators, supply voltage regulator circuits,buffer circuits, protective circuits, etc. The supply voltage regulatorcircuits may permit autonomous operation of the microprocessor in asupply system with an unregulated or excessive supply voltage. This maybe important for operation of the second functional unit, whose supplyvoltage may be adapted to the technology used, while, on the other hand,the original supply voltage may be retained for other electroniccircuits or measuring devices. Since the processing device may alsocontain memory devices, the write and erase voltages of the memorydevices may also be advantageously generated or adapted in the firstfunctional unit.

The division of the processing device into first and second functionalunits may allow a further technological development of the processingdevice without having to be taken into account from outside, providedthe technology is retained for the first functional unit. Furtherdevelopments of the technology may generally be associated with higherprocessing rates and lower voltage levels. Over the relatively longleads, the processing rates increase the interference potential to betaken into account. On the other hand, the higher processing ratespermit sequential processing for many processes for which parallelprocessing may have been previously necessary because of the lowerprocessing speed. Parallel processing generally necessitates paralleldata inputs and outputs, whereby the number of contact pads, and thusthe amount of chip area required, is increased. Thus, it may benecessary, despite the increasing functionality of the processors, notto let the number of contact pads increase in proportion thereto, but tolimit the increase. Accordingly, serial data input and output may bedesirable in the second functional unit. This, however, may requiresuitable conversion devices in the first functional unit.

If the matching circuits are not fixed, but instead are programmable,the flexibility may be even greater, since adaptation may then bepossible via a program. If the input and output levels of the processorchange because a new technology is used, the new voltage levels of thematching circuits may be adapted via the program.

These and other objects, features and advantages of the presentinvention will become more apparent in light of the following detaileddescription of preferred embodiments thereof, as illustrated in theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of a typical mount for a monolithic integratedcircuit according to the prior art;

FIG. 2 is a plan view of a typical mount for a hybrid circuit accordingto the prior art;

FIG. 3 is a plan view of a mount for a lateral arrangement of first andsecond functional units;

FIG. 4 is a plan view of a mount for a stacked arrangement of first andsecond functional units;

FIG. 5 is a plan view of a mount for a combination of a stackedarrangement and a lateral arrangement;

FIG. 6 is a plan view of a mount in which contacts of the first andsecond functional units are connected to a passive carrier; and

FIG. 7 is a cross-sectional view of a mount similar to FIG. 6, with theexternal terminals defined by an array of solder pads.

DETAILED DESCRIPTION OF THE INVENTION

Referring to FIG. 1, a monolithic integrated circuit 1 in a mountaccording to the prior art may have the mount comprise a molded plasticpackage 2. The carrier of the monolithic integrated circuit 1 may be aflat metal stamping or frame 3, which may provide the connections forthe contact pads of the monolithic integrated circuit 1 through theplastic package 2. The frame 3 may also include a platform 4 forreceiving the monolithic integrated circuit 1. The platform 4 may beconnected to an external ground pin. The contact pads of the monolithicintegrated circuit 1 may be connected to the associated inner leads ofthe frame 3 by bond wires. All of the external leads to the monolithicintegrated circuit 1 may be run via the frame 3.

Referring to FIG. 2, a prior art hybrid circuit may comprise twomonolithic integrated circuits 5, 6. As in FIG. 1, the carrier may be aframe 3 with a platform 4, and the two monolithic integrated circuits 5,6 may be arranged side by side on the platform 4. Contact may be made tothe monolithic integrated circuits 5, 6 via wire bonds which may runeither to the associated leads of the frame 3 or directly from circuitto circuit. In some cases, use may be made of a stacked structure, inwhich a smaller circuit may be cemented onto a larger circuit. Thesmaller circuit may generally be a memory circuit or a circuit withspecific components, such as capacitors, coils, filters, etc.

Hybrid circuits may usually be employed where subcircuits with differentbasic functions interact, for example an analog circuit and a digitalcircuit, possibly in conjunction with different memory types. In thismanner it may also be possible to combine products of differentmanufacturers. Mounts for hybrid circuits may also be entire printedcircuit boards, to which connections may also generally be made by wirebonding. The individual circuits and the wire bonds on the board maythen be protected by a plastic enclosure.

Referring to FIG. 3, a mount 2 has a lateral arrangement of first andsecond functional units 7, 8. Such a lateral arrangement of the twoseparate monolithic integrated circuit functional units 7, 8 may berelatively similar to the side-by-side arrangement of the two monolithicintegrated circuits 5, 6 of FIG. 2. The difference may be that in FIG.3, all external connections may be to the first functional unit 7 andthe second functional unit 8 may have connections to the firstfunctional unit 7. An exception may be a common ground connection viathe platform 4. If a frame 3 is used, the mount 2 may be limited torelatively few external leads, because the wire bonds may allow alimited bonding geometry, thus compensation by the design of theinternal frame leads may be partially possible. A remedy to this may beprovided by the stacked arrangement of FIG. 4.

In the stacked arrangement of FIG. 4, two or more subcircuits orfunctional units 7, 8 may be located on a frame platform 4 in a centralarrangement, which may allow the inner contacts of the frame 3 to beeasily reached from the edge of the first functional unit 7 via bondwires. Because of the stacked arrangement, the first functional unit 7may function as a carrier for the second functional unit 8, which mayrequire that the chip area of the first functional unit 7 be greaterthan the chip area of the second functional unit 8. The package outlineor the border of the plastic enclosure is represented by the line 2.

Referring to FIG. 5, an embodiment comprises a combination of a stackedarrangement and a lateral arrangement on a frame platform 4. The stackedarrangement may correspond to the stacked arrangement of FIG. 4, whilethe lateral arrangement may correspond to the lateral arrangement ofFIG. 3. The first functional unit 7 may support the second functionalunit 8 and may be connected laterally to an auxiliary unit 9 disposed onthe common frame platform 4. In this embodiment, connections to theoutside may be made via the first functional unit 7. The auxiliary unit9 may be a memory module, for example, that may be connected to thesecond functional unit 8 by bond wires or via the first functional unit7, depending on the spatial conditions. The package outline or theborder of the plastic enclosure is represented by the line 2.

Referring to FIG. 6, an embodiment of a mount 2 is illustrated in whicha possible problem of inadequate accessibility of the externalconnections 30 from the first functional unit 7 may be avoided by alateral arrangement of the first and second functional units 7, 8. Aninsulating carrier 10 comprising, for example, a ceramic body with aninterconnection plane 11 deposited on its surface may support the firstand second functional units 7, 8. The interconnection plane 11 maycomprise several, mutually isolated layers of wiring to form theinterconnections 12–17 and associated contact areas 20. By means of thewire bonds 40, connections may be made from the first and secondfunctional units 7, 8 to the contact areas 20 of the interconnections12–17. The interconnections 12–17 may be isolated from each other andfrom the surface, and may therefore cross arbitrarily or pass below thefirst or second functional units 7, 8, for example, the crossover ofinterconnections 15, 16, and the interconnection 17, which runs belowthe second functional unit 8. In this manner, the external terminals 30of the mount may be easily reached from the first functional unit 7. Thecarrier 10 may also be connected to the external terminals 30, or theterminals 30 may be embedded in the carrier 10 during manufacture. Theentire structure may be surrounded by a plastic enclosure 2.

Referring to FIG. 7, a mount comprises a carrier 10 and a lateralarrangement of the first and second functional units 7, 8, which issomewhat similar to FIG. 6. The mount of FIG. 7 differs from that ofFIG. 6 in that the external terminals may be defined by an array ofsolder pads 35. This may be used where the number of external terminalsis so high that with a linear arrangement of terminals along the edges,the spacing becomes too small. Each of the solder pads 35 may beconnected to a via hole 36, which may provide the electrical connectionto the interconnection plane 11. In FIG. 7, the wire bonds 40 from thefirst and second functional units 7, 8 to the interconnection plane 11are illustrated.

With the division of a processing device into first and secondfunctional units 7, 8, the mount 2 may not be limited to the use ofmonolithic integrated circuits. If appropriate, other manufacturingprocesses may be used for the individual subcircuits. It suffices thatwhen viewed from outside, a constant electrical performance of theprocessing device may be maintained which may be achieved by masking theprocessing device by means of a first functional unit having constantelectrical parameters.

Although the present invention has been shown and described with respectto several preferred embodiments thereof, various changes, omissions andadditions to the form and detail thereof, may be made therein, withoutdeparting from the spirit and scope of the invention.

1. A mount that contains a processing device which is divided into atleast a first functional unit and a second functional unit, and receivesa plurality of input signals and provides a plurality of output signals,comprising: a carrier that supports the processing device; where thefirst functional unit defines input and output interfaces of theprocessing device; where connections of the second functional unit areaccessible from outside the mount and the processing device via thefirst functional unit; and where the first functional unit includesmatching circuits which electrically match electrical characteristics ofthe input interfaces with electrical characteristics of the inputsignals, and match electrical characteristics of the output interfaceswith electrical characteristics of the output signal.
 2. The mount ofclaim 1, where the first functional unit and the second functional uniteach comprise an integrated circuit, the integrated circuits beingseparate.
 3. The mount of claim 2, where the carrier comprises a supportfor the separate integrated circuits of both the first and the secondfunctional units.
 4. The mount of claim 2, where the carrier comprises aframe that includes connections for contact pads of at least one of thefirst and second integrated circuits.
 5. The mount of claim 2, where atleast one supply terminal of the second functional unit is fed via thefirst functional unit.
 6. The mount of claim 2, where the carriercomprises a frame that includes a platform that receives at least one ofthe first and second integrated circuits.
 7. The mount claim 1, wherethe platform includes a connection to a ground potential.
 8. The mountof claim 1, where the mount comprises a molded plastic package.
 9. Themount of claim 1, where at least one of the matching circuits isprogrammable in terms of its electrical properties.
 10. The mount ofclaim 2, where the carrier comprises a frame that includes bond wiresthat connect a plurality of inner leads of the frame to each one of thetwo integrated circuits.
 11. The mount of claim 2, where the twointegrated circuits are arranged laterally.
 12. A mounting arrangementfor a processing device that receives a plurality of input signals andprovides a plurality of output signals, comprising: a mount for theprocessing device, the processing device being divided into at leastfirst and second functional units that are separate from each other,each of the first and second functional units being embodied in anintegrated circuit, the mount supporting the integrated circuits of thefirst and second functional units, the first functional unit defininginput and output interfaces of the processing device, connections of thesecond functional unit being routed through the first functional unit,the first functional unit including matching circuits that matchelectrical characteristics of the input interfaces with electricalcharacteristics of the input signals and match electricalcharacteristics of the output interfaces with electrical characteristicsof the output signal.
 13. The mounting arrangement of claim 12, wherethe carrier comprises a frame.
 14. The mounting arrangement of claim 13,where the frame includes connections for contact pads of at least one ofthe first and second integrated circuits.
 15. The mounting arrangementof claim 13, where the frame includes a platform that receives at leastone of the first and second integrated circuits.
 16. The mountingarrangement of claim 12, where the first and second functional units arearranged laterally.
 17. The mounting arrangement of claim 12, where thefirst and second functional units are in a stacked arrangement.
 18. Themounting arrangement of claim 12, further comprising an auxiliary unit,where the first and second functional units are in a stackedarrangement, where the stacked arrangement and the auxiliary unit are ina lateral arrangement.
 19. The mounting arrangement of claim 12, furthercomprising an insulating carrier having an interconnection plane, wherethe insulating carrier supports the first and second functional units,the interconnection plane having a plurality of mutually isolated layersof wiring that form interconnections between the first and secondfunctional units.
 20. The mounting arrangement of claim 19, where themount includes a plurality of external terminals that connect with thefirst functional unit.
 21. An integrated circuit that receives aplurality of input signals and provides a plurality of output signals,comprising: a package; a first die comprising a plurality of matchingcircuits that receive the input signals and second die output signals,and provide compensated input signals and the output signals; and asecond die that comprises a processing element and receives thecompensated input signals and provides the second die output signals;wherein the matching circuits match the electrical characteristics ofthe input signals with the electrical characteristics of the compensatedinput signals, and match the electrical characteristics of the outputsignals and the second die output signals.
 22. The integrated circuit ofclaim 21, wherein the matching circuits are programmable.